4-33 fast and ls ttl data dual d-type positive edge-triggered flip-flop the mc54/74f74 is a dual d-type flip-flop with direct clear and set inputs and complementary (q, q ) outputs. information at the input is transferred to the outputs on the positive edge of the clock pulse. clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. after the clock pulse input threshold voltage has been passed, the data input is locked out and information present will not be transferred to the outputs until the next rising edge of the clock pulse input. ? esd > 4000 volts 13 14 12 11 10 9 8 2 1 3 4 5 6 7 gnd v cc c d2 d 2 cp 2 s d2 q 2 q 2 c d1 d 1 cp 1 s d1 q 1 q 1 connection diagram cp 1 d 1 s d1 c d1 q 1 q 1 d 2 cp 2 c d2 s d2 q 2 q 2 function table (each half) input outputs @ t n @ t n + 1 d q q l l h h h l h = high voltage level l = low voltage level t n = bit time before clock pulse t n + 1 = bit time after clock pulse j suffix ceramic case 632-08 n suffix plastic case 646-06 d suffix soic case 751a-02 mc54fxxj ceramic mc74fxxn plastic mc74fxxd soic mc54/74f74 dual d-type positive edge-triggered flip-flop fast ? schottky ttl 14 1 14 1 ordering information 14 1 logic symbol 4 5 6 3 2 1 10 12 11 8 9 13 v cc = pin 14 gnd = pin 7 s d1 d 1 cp 1 q 1 q 1 c d1 s d2 d 2 cp 2 q 2 q 2 c d2 asynchronous inputs: low input to s d sets q to high level low input to c d sets q to low level clear and set are independent of clock simultaneous low on c d and s d makes both q and q high
4-34 fast and ls ttl data mc54/74f74 q s d q d cp c d logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 54, 74 4.50 5.0 5.50 v t a operating ambient temperature range 54 55 25 125 c a 74 0 25 70 i oh output current e high 54, 74 1.0 ma i ol output current e low 54, 74 20 ma dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage v il input low voltage 0.8 v guaranteed input low voltage v ik input clamp diode voltage 1.2 v i in = 18 ma v cc = min 54, 74 2.5 3.4 v i oh = 1.0 ma v cc = 4.50 v v oh output high voltage 74 2.7 3.4 v i oh = 1.0 ma v cc = 4.75 v v ol output low voltage 0.35 0.5 v i ol = 20ma v cc = min i ih input high current 20 m a v in = 2.7 v v cc = max 100 m a v in = 7.0 v i il input low current (cp and d inputs) 0.6 ma v in = 0.5v v cc = max (c d and s d inputs) 1.8 ma i os output short circuit current (note 2) 60 150 ma v out = 0 v v cc = max i cc power supply current 10.5 16 ma v cp = 0 v v cc = max notes: 1. for conditions shown as min or max, use the appropriate value specified under guaranteed operating ranges. 2. not more then one output should be shorted at a time, nor for more than 1 second.
4-35 fast and ls ttl data mc54/74f74 ac characteristics 54/74f 54f 74f t a = +25 c t a = 55 c to +125 c t a = 0 c to 70 c v cc = +5.0 v v cc = 5.0 v 10% v cc = 5.0 v 10% c l = 50 pf c l = 50 pf c l = 50 pf symbol parameter min max min max min max unit f max maximum clock frequency 100 100 100 mhz t plh propagation delay 3.8 6.8 3.8 8.5 3.8 7.8 ns t phl cp n to q n or q n 4.4 8.0 4.4 10.5 4.4 9.2 ns t plh propagation delay 2.5 6.1 2.5 8.0 2.5 7.1 ns t phl c dn or s dn to q n or q n 3.5 9.0 3.5 11.5 3.5 10.5 ns ac operating requirements 54/74f 54f 74f t a = +25 c t a = 55 c to +125 c t a = 0 c to +70 c v cc = +5.0 v v cc = 5.0 v 10% v cc = 5.0v 10% symbol parameter min typ max min max min max unit t s (h) setup time, high or low 2.0 3.0 2.0 t s (l) d n to cp n 3.0 4.0 3.0 ns t h (h) hold time, high or low 1.0 2.0 1.0 ns t h (l) d n to cp n 1.0 2.0 1.0 t w (h) cp n pulse width, high 4.0 4.0 4.0 ns t w (l) or low 5.0 6.0 5.0 ns t w (l) c dn or s dn pulse width, low 4.0 4.0 4.0 ns t rec recovery time c dn or s dn to cp 2.0 3.0 2.0 ns
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